Many current electronic products rely upon low power or battery powered operation of one or more integrated circuits (ICs). These integrated circuits can be used in a wide variety of low-power/battery-operated applications including, for example, silicon-on-insulator (SOI) technology solutions, multi-core microcontrollers, or other low-power/battery-operated applications. Typically, some processing cores are high performance with high-power operation requirements, and other cores are lower performance with low-power operation requirements or very low-power operation requirements. SOI technologies provide dedicated device options for each case. High-performance cores are implemented with LVT (low threshold voltage) devices, and low-power cores are implemented using RVT (regular threshold voltage) devices.
For both LVT devices and RVT devices, back-biasing (BB) techniques are used to adjust the trade-off between performance and power for the RVT cores or the LVT cores. This trade-off is adjusted based upon whether a particular core is operating in a high-performance mode or in a low-power mode. RVT devices support a wide range of reverse back-biasing (RBB) voltages that allow power consumption to be significantly decreased at a given performance cost. LVT devices support a wide range of forward back-biasing (FBB) voltages that allow performance to be increased at a given power cost. In both cases, BB voltage levels may be set beyond the supply rails for the IC. As such, negative voltage charge pumps (NCPs) are employed to move BB voltage levels below the low-voltage supply rail voltage, and positive voltage charge pumps (PCPs) are employed to move BB voltage levels above the high-voltage supply rail voltage.
Prior BB solutions, however, suffer from various problems including the need for external capacitors. The need for external capacitors, for example, leads to an increase of system cost due to additional discrete components and package pins required to implement the external capacitors. Further, two different and dedicated circuit solutions are typically implemented, one to bias the RVT cores and another to bias the LVT cores. In addition, logic processing must typically be stopped during back-bias level transitions because different well voltages for the RVT cores and LVT cores are not sufficiently symmetrical during such transitions. As such, this stoppage in logic processing is required to support logic activity without the risk of timing violations. This stopping and restarting of logic processing, however, leads to increased power consumption and processing delays.